At the lower bus speeds of today's processors, the current methodology to gain observe-ability of the bus signals is to install a probe interposer assembly 102 between the processor socket 104 and the motherboard socket 106, as illustrated in FIG. 1. The interposer assembly is typically wired to “tap-off” a small amount of energy from each bus signal such that the actual bus is minimally perturbed and may operate normally at full speed. The small amount of energy which gets “tapped off” for each signal in the interposer assembly is routed by cable 108 to components which recover those signals and allow them to be conditioned to make them coherent for purposes of analyzing what is happening on the bus when failures occur.
Improvements in the bus observe-ability/probing methodology are desired in view of the higher bus speeds in development today, which “break” the current “tap-off” bus observe-ability/probing methodology.